About Company
As a Physical Design Engineer, you will take the lead in planning, designing, and validating Power Delivery Networks (PDN) for System-on-Chip (SoC) architectures and custom IPs. Your primary tool for implementation will be Fusion Compiler. You will act as a central collaborator, working with IP partition owners, reliability leads, and specialized IR/EM/power integrity engineers to translate power requirements into robust, high-performance silicon solutions..
Job Details
| Role: | Physical Design Engineer |
| Salary: | UP to ₹15 LPA* |
| Location: | Bengaluru |
| Job Type: | fulltime |
| Posted Date: | 07/02/2026 |
| Application Deadline: | Apply Soon |
Job Description
As a Physical Design Engineer, you will take the lead in planning, designing, and validating Power Delivery Networks (PDN) for System-on-Chip (SoC) architectures and custom IPs. Your primary tool for implementation will be Fusion Compiler. You will act as a central collaborator, working with IP partition owners, reliability leads, and specialized IR/EM/power integrity engineers to translate power requirements into robust, high-performance silicon solutions.
Requirements
- Minimum Requirements:
- Education & Experience: * BTech in Electrical/Electronics Engineering with 3+ years of relevant experience.
- OR MTech in VLSI or a related field with 2+ years of relevant experience.
- Tool Expertise: Proven experience using Synopsys Fusion Compiler.
- Domain Skills: Core technical proficiency in Physical Design (PD) flows.
- Preferred Skills:
- Automation: Scripting proficiency in TCL for workflow automation.
- Specialization: Deep expertise in PDN design and implementation.
- Verification: Advanced experience in layout design and verification cleanup using Fusion Compiler (FC) or ICC.
Roles and Responsibilities
- PDN Architecture: Plan and design power networks for complex SoCs and IPs using Synopsys Fusion Compiler.
- Layout Verification: Execute layout verification and ensure the PDN is 100% clear of all DRCs (Design Rule Checks).
- Technical Collaboration: Partner with IR/reliability owners and power integrity engineers to gather constraints and implement them into the physical layout.
- Optimization: Balance performance, reliability, and silicon area to meet aggressive design goals.
- Efficiency: Implement “best-known methods” (BKMs) to produce high-quality layouts within tight project timelines.
How to Apply?
Role Summary
This position is a specialized niche within Physical Design. While a general PD engineer handles the entire “Netlist-to-GDSII” flow, this role focuses specifically on the Power Delivery Network (PDN). You are the “electrical architect” of the chip, ensuring that every transistor receives the correct voltage without excessive “noise” or heat. In the era of 2nm and 3nm chips, PDN design is one of the most difficult and critical bottlenecks in semiconductor engineering.
Company Culture & Insights
Intel is currently undergoing a massive transformation into Intel Foundry, aiming to compete directly with TSMC. This means the culture in Bangalore is shifting from “internal-only” design to a service-oriented foundry model. It is a high-pressure environment with a heavy emphasis on “First Time Right” silicon. Intel is known for its rigorous documentation and proprietary methodologies (BKMs), which provide a very structured way to learn VLSI.
Why We Recommend This Job
- AI-Era Relevance: High-performance AI chips require incredibly complex power grids. Mastering PDN design now makes you a “high-value” asset for any company building AI hardware.
- Tool Mastery: Synopsys Fusion Compiler is the industry’s leading “AI-driven” EDA tool. Gaining deep expertise in it is a major career booster.
- Intel Foundry Exposure: You will get to work on the most advanced process nodes (Intel 18A and beyond) before they are available to the general public.
Career Growth Potential
Starting as a PDN specialist allows you to pivot into Power Integrity (PI) Engineering or SoC Integration Lead roles. Because this is a Contract Employee role, it serves as a common entry point for full-time conversion at Intel or as a launchpad into other “Big Tech” firms (Apple, Nvidia, Google) that are desperately seeking engineers who understand power delivery at advanced nodes.
Skills You’ll Gain
- IR-Drop & EM Analysis: Understanding how voltage drops across the chip and how to prevent “Electromigration” (wires melting over time).
- Fusion Compiler (FC) Expert Level: Advanced knowledge of Synopsys’ flagship physical design suite.
- Foundry-Level Verification: Learning the strict rules required to manufacture chips at the world’s most advanced fabrication plants.
Salary & Benefits Info
- Estimated Salary: For a contract role with 2–4 years of experience, the Total Compensation (TC) in Bangalore typically ranges from ₹15,00,000 to ₹25,00,000 per annum. While contract roles sometimes lack the stock options (RSUs) of full-time roles, the base pay is often higher to compensate.
- Benefits: * Hybrid Model: Flexibility to work from home part-time.
- Intel Perks: Access to Intel’s massive internal learning library and world-class office facilities in Bangalore.
- Intel Diversity Statistics
- Intel is highly transparent regarding its workforce composition. According to their 2024-2025 Global Diversity and Inclusion Report:
- Gender: Women represent 25.2% of the global workforce and 19.8% of technical roles.
- US Workforce (Racial Breakdown):
- Asian: 40.2%
- White: 43.1%
- Hispanic: 9.8%
- Black: 5.1%
- Intel has a public goal to increase the number of women in technical roles to 25% by 2030.