Synopsys – Hiring for Staff Engineer – Physical Design & Signoff @Bangalore

About Company

Synopsys is at the heart of the “Era of Pervasive Intelligence.” As a Staff Engineer, you will be a primary driver in the Electronic Design Automation (EDA) space, developing state-of-the-art RTL to GDS implementations. This role is unique: you aren’t just using the tools; you are perfecting the methodology for Silicon Lifecycle Management (SLM) monitors—on-chip sensors that monitor PVT (Process, Voltage, Temperature) and silicon biometrics.

Job Details

Job Description

The Staff Engineer role at Synopsys is a “Power User” position. You are designing the SLM (Silicon Lifecycle Management) IP that the rest of the world (Apple, NVIDIA, Intel) will put into their chips. This isn’t just about moving pixels; it’s about Silicon Biometrics. You are building the “nervous system” of the chip that allows it to report its own health, aging, and voltage glitches while in a self-driving car or a data center.

Requirements

• Education: BS/B.Tech or MS/M.Tech in Electrical Engineering.
• Experience: 5+ years of relevant industry experience in Physical Design and Signoff.
• Tool Proficiency: Expertise in Synopsys tools: Fusion Compiler (FC), PrimeTime (PT/PT-PX), ICV, and VCLP.
• Node Expertise: Proven track record of successful tape-outs in nodes from 14nm down to 2nm.
• Technical Depth: Deep understanding of OCV, POCV, derates, crosstalk, and multi-voltage (UPF) design.

Roles and Responsibilities

• Full Flow Implementation: Execute the complete Digital BE (Back-End) flow: synthesis, floorplanning, power planning, placement, CTS (Clock Tree Synthesis), and routing.
• Silicon Monitoring: Design and productize on-chip monitors for glitch, droop, and silicon biometrics.
• Signoff Excellence: Lead timing signoff (Post-layout STA), functional ECO development, and high-frequency IP closure.
• Physical Verification: Own the “deck” for DRC, LVS, PERC, ERC, Antenna, and EMIR/Power signoff.
• Advanced Nodes: Drive timing closure and model characterization for advanced FinFET and GAA (Gate-All-Around) processes (3nm, 2nm).
• Methodology & Scripting: Create and enhance flows using TCL and PERL to optimize Performance, Power, and Area (PPA).

How to Apply?

Role Summary

The Staff Engineer role at Synopsys is a “Power User” position. You are designing the SLM (Silicon Lifecycle Management) IP that the rest of the world (Apple, NVIDIA, Intel) will put into their chips. This isn’t just about moving pixels; it’s about Silicon Biometrics. You are building the “nervous system” of the chip that allows it to report its own health, aging, and voltage glitches while in a self-driving car or a data center.

Company Culture & Insights

Synopsys is the “Gold Standard” of EDA. The culture is technically rigorous and academic in its depth, but fast-paced in its execution. In the Bengaluru office, you will be surrounded by the architects of the tools you use. This provides an unmatched feedback loop—if you find a limitation in Fusion Compiler, you can talk directly to the R&D team that wrote the code.

Why We Recommend This Job

• GAA Process Exposure: You will be working on Gate-All-Around (GAA) transistors (2nm), which is the most advanced semiconductor structure on Earth.
• SLM Specialization: Silicon Lifecycle Management is a booming field as chips become more expensive and “health monitoring” becomes mandatory for automotive safety.
• Prestige: A “Staff” title at Synopsys is highly respected globally and often equivalent to a “Principal” role at smaller design houses.

Career Growth Potential

From an Associate level, you are on a fast track toward Senior QA Automation Engineer or SDET (Software Development Engineer in Test). Given Siemens’ focus on HPC and AI, this role provides an excellent bridge into DevOps Engineering or Performance Engineering roles.

Skills You’ll Gain

• GraphQL Testing: Mastering the nuances of testing flexible, high-speed API layers.
• Containerized Testing: Learning how to validate software running inside Kubernetes pods.
• CI/CD Automation: Moving beyond manual scripts to “Continuous Testing” integrated into the deployment pipeline..

Salary & Benefits Info

• Estimated Salary: For a Staff Engineer (5+ years) in Bengaluru, the Total Compensation (TC) typically ranges from ₹45,00,000 to ₹75,00,000+ per annum, including a significant RSU (Stock) component.
• ESPP: A standout benefit—buy Synopsys stock at a 15% discount with a 24-month look-back period.
• Growth: “FTO” (Flexible Time Off) and extensive maternity/paternity support are standard.

Frequently Asked Interview Questions

Technical Questions (Physical Design & Low Power)

1. GAA Transistors: “How does the transition from FinFET to Gate-All-Around (GAA) at 2nm affect your power planning and IR drop analysis?”
2. STA/Signoff: “Explain how POCV (Parametric On-Chip Variation) differs from traditional AOCV. How do you handle setup/hold margins at the 3nm node?”
3. UPF/Power: “In a multi-voltage design, how do you handle level shifters and isolation cells during the synthesis stage to ensure the UPF intent is preserved?”
4. ECO Flow: “Walk me through your process for generating a timing ECO. How do you ensure that fixing a setup violation doesn’t create a new hold or DRC violation?”

Behavioral & Culture Questions

1. Problem Solving: “Describe a time you encountered a ‘un-routable’ block due to congestion. What creative floorplanning changes did you implement to solve it?”
2. Collaboration: “As a Staff Engineer, you often sit between Architects and Physical Designers. How do you resolve a conflict where the architectural goals for frequency make physical closure impossible?”
3. Innovation: “Synopsys values proactive innovation. Tell me about a script or flow enhancement you developed that saved your team significant turnaround time (TAT).”