Global information technology and consulting service leader Wipro Limited is hiring through its specialized hiring initiative Elite VLSI under Job Requisition ID: 203748. Hosted on Wipro’s official careers portal (careers.wipro.com), this full-time role offers engineering opportunities across Wipro’s semiconductor and VLSI engineering hubs in Bengaluru, Hyderabad, Pune, and Kochi, India.
This program specifically targets fresh engineering graduates and early-career talent specializing in VLSI, Microelectronics, System-on-Chip (SoC) design, RTL verification, and Embedded Systems.
Job Details
| Attribute | Information |
| Role Title | Project Engineer – Elite VLSI |
| Job Requisition ID | 203748 |
| Company Entity | Wipro Limited |
| Business Unit / Group | Engineering Edge / VLSI & Semiconductor Solutions |
| Work Location | Bengaluru |
| Employment Type | Full-Time, Permanent |
| Experience Required | 0 to 2 Years / Freshers |
| Posting Date | October 2026 |
| Application Deadline | Immediate / Rolling Basis |
About Company
Wipro Limited is a leading global technology services and consulting company delivering innovative digital, cloud, engineering edge, and semiconductor solutions.
Wipro’s VLSI & Semiconductor Engineering Edge unit collaborates with major global fabless semiconductor firms, silicon foundries, and consumer electronics giants. The team delivers end-to-end chip design services—spanning RTL design, functional verification, physical design, DFT (Design for Testability), and analog layout design.
Comprehensive Job Overview
As a Project Engineer – Elite VLSI, you will be part of core engineering design teams working on next-generation ASIC, FPGA, and System-on-Chip (SoC) projects.
In this role, you will participate in digital logic design, functional testbench development using SystemVerilog/UVM, physical synthesis, static timing analysis (STA), or embedded firmware development. Candidates undergo intensive domain-specific training at Wipro before deployment on live global semiconductor client projects.
Requirements & Qualifications
1. Educational Eligibility Criteria
- Degree: Bachelor’s degree (B.E. / B.Tech) or Master’s degree (M.E. / M.Tech / M.S.) in:
- Electronics & Communication Engineering (ECE)
- Electrical & Electronics Engineering (EEE)
- VLSI / Microelectronics Design
- Telecommunication Engineering
- Academic Threshold: Minimum 60% or 6.0 CGPA in 10th, 12th, Graduation, and Post-Graduation (no active backlogs at the time of joining).
2. Core Technical Skills
- Hardware Description Languages (HDLs): Solid foundational understanding of Verilog, SystemVerilog, or VHDL.
- Digital Design Concepts: In-depth clarity on combinational and sequential logic design, finite state machines (FSM), flip-flops, setup/hold times, clock domain crossing (CDC), and memory architectures.
- Verification Frameworks: Familiarity with functional verification principles, coverage-driven verification, and basic exposure to UVM (Universal Verification Methodology) is a strong plus.
- Scripting Languages: Basic programming or scripting capabilities in Python, Perl, Tcl, or C/C++ for automation in EDA tool flows.
- EDA Tools Exposure: Coursework or project experience using industrial or academic EDA tools (Cadence, Synopsys, Siemens EDA / ModelSim).
3. Soft Skills
- Strong analytical, mathematical, and logical problem-solving capabilities.
- Clear written and verbal English communication skills for collaborating in multi-disciplinary chip design teams.
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Key Roles and Responsibilities
- RTL Design & Logic Synthesis: Assist in writing, optimizing, and synthesizing clean synthesizable Verilog/SystemVerilog RTL code for digital logic modules.
- Functional Verification: Develop testbenches, write assertions (SVA), and execute simulation test cases to verify logic correctness against specification documents.
- Physical Design & STA Assistance: Support floorplanning, placement and routing (P&R), clock tree synthesis (CTS), static timing analysis (STA), and layout parameter extraction.
- Automation & Scripting: Write Tcl, Python, or Perl scripts to automate simulation runs, regression tracking, and EDA tool reports.
- Continuous Skill Enhancement: Complete specialized Wipro VLSI training modules on cutting-edge sub-node silicon technologies.
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Technical Tools & Skill Summary
| Operational Domain | Tools, Languages & Methodologies |
| HDLs & Languages | Verilog, SystemVerilog, VHDL, C/C++ |
| Scripting & Shell | Python, Tcl, Perl, Bash |
| EDA Tool Suites | Cadence (Virtuoso/NC-Sim), Synopsys (Design Compiler/VCS), Siemens (ModelSim) |
| Domain Methodologies | RTL Design, UVM Verification, STA, DFT, ASIC/FPGA Flow |
| Concepts | Digital Logic, FSM, Clock Domain Crossing, Setup/Hold Time |
Compensation & Benefits
- Estimated Salary Package: Competitive entry-level engineering package (typically ranging from ₹4.5 LPA to ₹6.5 LPA for Elite VLSI graduates, including performance incentives and retention bonuses).
- Work Location: Major Wipro technology centers in Bengaluru, Hyderabad, Pune, or Kochi.
- Health & Insurance: Group medical insurance covering employee and dependents, term life insurance, and personal accident insurance.
- Career Development: Fast-track career path in semiconductor engineering, sponsored higher education certifications, and hands-on exposure to advanced silicon nodes (7nm, 5nm, 3nm).
Selection & Recruitment Process
- Online Aptitude & Coding Test:
- Logical Reasoning, Quantitative Aptitude, and Verbal Ability.
- Written English Communication test (Essay writing evaluation).
- Technical assessment covering Digital Electronics, C Programming, and Verilog/VLSI basics.
- Technical Interview Round 1: In-depth evaluation of Digital Logic Design, state machines, timing diagrams (setup/hold constraints), Verilog syntax, and academic VLSI projects.
- Technical Interview Round 2 (Project & Advanced VLSI): In-depth discussion on SystemVerilog/UVM, scripting, FPGA/ASIC flow steps, and hardware debugging scenarios.
- HR Round: Final discussion assessing communication skills, willingness to relocate to designated job locations, shift flexibility, and background verification.
How to Apply?
- Click on the official Wipro careers application link provided below.
- Click Apply and register or log in to your Wipro Applicant portal account.
- Confirm Job Requisition ID: 203748 for Project Engineer – Elite VLSI.
- Complete your educational profile details, upload an updated resume highlighting VLSI projects, Verilog skills, and academic scores, and submit your application.
Official Application Link: Apply Link