Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kurnool, an Institute of National Importance under the Ministry of Education, Govt. of India, invites applications for 02 temporary positions of Junior Research Fellow (JRF) under the MeitY-sponsored C2S Project (Category III).
Job Details
| Attribute | Information |
| Hiring Institution | IIITDM Kurnool, Andhra Pradesh |
| Open Position | Junior Research Fellow (JRF) – 02 Posts |
| Department | Electronics and Communication Engineering (ECE) |
| Project Title | Instruction-Data level Parallelism based Hardware Accelerator Design in HPC and CPS Applications |
| Sponsoring Agency | Chips to Startup (C2S) Programme (Category III), MeitY, Govt. of India |
| Chief Investigator (CI) | Dr. Mohamed AsanBasiri M |
| Consolidated Salary | • With GATE score: ₹37,000 per month • Without GATE score: ₹30,000 per month |
| Nature & Duration | Purely temporary for 01 year (extendable up to 1–2 years based on performance & funds) |
| Location | Jagannathagattu, Dinnedevarapadu, Kurnool, Andhra Pradesh – 518008 |
| Application Deadline | 28th August 2026 |
About Institution
IIITDM Kurnool is an autonomous premier institute established by the Ministry of Education, Govt. of India, to provide high-quality education and research in Information Technology, Design, and Manufacturing.The Department of Electronics and Communication Engineering leads advanced research in Digital VLSI, Hardware Acceleration, High-Performance Computing (HPC), Cyber-Physical Systems (CPS), and Microelectronics.
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Job Description
The Junior Research Fellow (JRF) will contribute to designing instruction-data level parallelism hardware accelerators tailored for High-Performance Computing (HPC) and Cyber-Physical Systems (CPS) applications.Key tasks include RTL coding, system-level architecture design, IP integration using Xilinx Vivado, custom IP design, and semi-custom ASIC synthesis using EDA tools.
Requirements & Required Qualifications
1. Minimum Qualification & Experience
- Option A: B.E. / B.Tech in Electrical / Electronics Engineering with CGPA $\ge 6.5$ (or equivalent).
- Option B: B.E. / B.Tech in Electrical / Electronics Engineering with CGPA $\ge 6.5$AND M.E. / M.Tech in Microelectronics / VLSI Design with CGPA $\ge 6.5$.
2. Desirable Qualification & Experience
- Direct experience in Digital System Design and RTL design using Verilog/VHDL.
- Hands-on expertise in IP Integration and Custom IP development using Xilinx Vivado.
- Practical familiarity with Semi-Custom ASIC design flows using standard EDA tools.
Roles and Responsibilities
- Hardware Accelerator Architecture:Design and optimize Instruction-Data level Parallelism (IDLP) based hardware blocks for HPC/CPS environments.
- RTL & IP Development:Write, simulate, and synthesize Verilog/VHDL code for custom microarchitectures and integrate IP modules in Xilinx Vivado.
- ASIC & FPGA Implementation:Perform semi-custom ASIC synthesis and timing/power analysis using EDA tools alongside FPGA prototyping.
- Documentation & Reporting:Assist the Chief Investigator in drafting progress reports, research publications, and technical documentation.
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Skills You’ll Gain
| Category | Specific Tools & Competencies Mastered |
| RTL & HDL Design | Verilog, VHDL, Structural & Behavioral Modeling. |
| FPGA Prototyping | Xilinx Vivado, Custom IP Core Integration, Hardware Debugging. |
| ASIC EDA Tools | Cadence / Synopsys / Mentor Synthesis, Timing Analysis, Semi-Custom Layout. |
| Parallel Architectures | Instruction-Data Level Parallelism (IDLP), HPC & Cyber-Physical Systems Acceleration. |
Application Procedure & Selection Process
- Submission Deadline:On or before 28th August 2026.
- Mode of Application:
- By Email:Send scanned copy of the duly filled and signed application form along with self-attested testimonials/certificates as a single PDF to asan@iiitk.ac.in with the subject line
Research Associate-1: 63/2026/JRF Application: IIITDMKL/ECE/JRF/2026/02. - By Post: Send hard copies to:
Dr. Mohamed AsanBasiri MChief Investigator, Department of ECE,IIITDM Kurnool, Jagannathagattu,Dinnedevarapadu, Kurnool, Andhra Pradesh – 518008.
- By Email:Send scanned copy of the duly filled and signed application form along with self-attested testimonials/certificates as a single PDF to asan@iiitk.ac.in with the subject line
- Selection Mode:Written Test followed by Interview for shortlisted candidates (communicated via email).
- Official Notification PDF:Download PDF Link
Frequently Asked Interview Questions (With Answers & Solution Guidelines)
Instruction-Data Level Parallelism (IDLP) in VLSI
- Question:“What is the structural difference between Instruction-Level Parallelism (ILP) and Data-Level Parallelism (DLP), and how do you implement both in a domain-specific hardware accelerator?”
- Answer & Solution Context: Focus on superscalar/pipelined execution for ILP vs. SIMD/vector processing units for DLP. Explain combining pipelined fetch/decode controllers with parallel execution lanes sharing common memory bandwidth.
FPGA IP Integration & Synthesis
- Question:“How do you handle clock domain crossing (CDC) issues when integrating custom IPs with third-party bus protocols (e.g., AXI4) in Xilinx Vivado?”
- Answer & Solution Context: Detail dual-clock FIFOs, multi-flop synchronizers, handshaking logic mechanisms, and configuring Xilinx IP Integrator constraints (
set_clock_groups) to avoid metastability during hardware synthesis.